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ADuCM360 wrong timer period.

Question asked by rvictor on Apr 16, 2018
Latest reply on Apr 19, 2018 by barryzhang

ADuCM360 wrong timer period.


I am trying to implement signal generator on ADuCM360 using DAC+DMA with TIMER1 as DMA activation source. The microcontroller is running on 16 MHz, timer is configured for PCLK as source clock and divider 1. DMA is working with 64 values and I monitor the DMA interrupt for timing.

The first problem is that the timer clock seems to be prescaled by factor of 4 even if I use PCLK and prescaler 1.

The second problem is: with time LD value of 7 I should get timer interval of 1.75 microseconds (with prescaler of 4) which should after 64 activation of DMA transfer trigger the DMA interrupt with interval of 112 microseconds. But I observe 127.2 microseconds. The direct timer interrupt monitoring also demonstrates large difference in measured interval for low LD values.

So question is if I am missing something here or how this behavior can be explained.


Thank you