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AD9910: can't control externally

Question asked by irenevg on Apr 16, 2018
Latest reply on Apr 24, 2018 by irenevg



Fistly, I used the AD9910 evaluation board software to control it. I used an external clock of 25 MHz, checked the "/2 Divider Disable" and enabled the multiplier with a multriplier of 40. Thus, I had a system clock of 1000 MHz. I used the corresponding components to use the PLL filter and the external clock instead of the XTAL.

Everything works well with the software (the filtered output, the sync clk, single tone, etc.). My problem become when I try to control externally. I set jumpers W1, W2 and W4 to disable and I remove W5, W6 and W3 jumpers (W7 -> REF_CLK and W11 -> HI).


I'm using a pic32 to control it. My connections between the AD9910 and the pic32 are:

Master Reset -> pic32 (digital pin)

IO_update -> pic32 (digital pin)

SDIO -> pic32 (SPI)

SCLK -> pic32 (SPI)

CSB -> pic32 (digital pin)

IO_reset -> ground

EXT_PWR_DWN -> ground

P_2, P_1, P_0 -> ground (use profile 0)

DRHOLD, DR_CTL -> ground


My pseudocode is:

Master Reset: LOW - HIGH - LOW (registers default value)

CFR1: 0x00, 0x00, 0x00, 0x00 (SDIO, MSB...)

IO_Update: LOW - HIGH - LOW (update values from buffer to registers)

CFR2: 0x00, 0x40, 0x08, 0x20 (SYNC_CLK enable)

IO_Update: LOW - HIGH - LOW

CFR3: 0x1D, 0x3F, 0xC1, 0x50 (Values to control my system clock)

IO_Update: LOW - HIGH - LOW

(I know that I could only use the IO_update once I finished to write, but I tried to and neither works)


My SYNC_CLK is always 3.1 MHz (with my configuration it shoul be 250 MHz). I try to disable this output by CFR2[22]=0, but still having 3.1 MHz signal. I don't know if i'm doing something wrong, but the registers have the same value as in the PC software, and the IO_Update pulse width is greater than SYNC_CLK pulse width.


Sorry for my poor english.

Thank you in advance.