trying to determine cause of VisualAnalog error message
ADC Data Capture: Invalid Core selection state in register 0x09:00
Please check and let me know the following:
1. Please read register 0x056F to check PLL status.
2. What is the input clock rate?
3. Is clock divider used?
4. What is the LMF configuration?
5. What is register 0x056E set to?
Retrieving data ...