if a clock signal with frequency of fclk and jitter of tj_clk input to a frequency divider, the output frequency is fclk/N.

if the divider is with jitter of tj_div, then the jitter of the output signal is root(tj_clk^2+tj_div^2) , am I right?

is there anything else(related to N) to the output jitter?

thanks.

Dear xfine,

Your formula is correct to a first order, and it's a bit diffcult to improve on that without getting a lot more sophisticated.

Your formala assumes that all of the random jitter is uncorrelated, which as I said, is a reasonable assumption.

If you divide the signal frequency down, it's possible to be affected by the noise floor of the driver. For instance, if one of our parts has 300 fs of random jitter at Fout=200MHz, and I then change the output divider so that Fout=10MHz, I may see more than 300 fs of jitter just because I've reached the noise floor of the output driver. Therefore, it's possible for the same part to have a different amount of additive jitter.

You may also encounter the issue of not being able to integrate over the same range of the phase noise plot for the lower output frequency. For instance, it's not meaningful to intgerate the phase noise from 12kHz-20MHz for a 10MHz clock.Integration of phase noise stops at half of the carrier frequency.

All that said, assuming that none of the above is an issue, your approximation is correct.

-Paul Kern