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how does frequency divider influence clock jitter?

Question asked by xfine on Dec 11, 2011
Latest reply on Dec 16, 2011 by pkern

if a clock signal with frequency of fclk and jitter of tj_clk  input to a frequency divider, the output frequency is fclk/N.

if the divider is with jitter of tj_div, then the jitter of the output signal is root(tj_clk^2+tj_div^2) , am I right?

is there anything else(related to N) to the output jitter?