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ad9361 spi_clk rate change

Question asked by DawnLaw on Apr 11, 2018

In our design,  first we use the arm to config the ad9361 using spi_clk no more than 10MHz. It worked.  Then we let the PL to take over the spi interface(we made a little switch in fpga PL), using a 40MHz spi_clk., because we need to change some regs in ad9361 in real time,  the fast the better.  It worked too. But the problems is,  when we switched back to the arm spi, It stopped working, both write and read operations failing.  At this point,  we switched back to PL again, It is still working.  So we assume, the switching somehow broke the arm SPI. But, when using the ILA to capture the four spi signals from/to the ARM,  the timing is corret, spi_clk, spi_enb,  spi_mosi, all present as expected.  however,  the ARM SPI just won't work.  Can anybody please tell me what is the problem here?  

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