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jesd_core.c is mismatched with ADI JESD IP

Question asked by Even_Chow on Apr 10, 2018
Latest reply on Apr 10, 2018 by Even_Chow

I'm working with AD9371 eval board and zynq ZC706. I want to add my own FPGA  IP into the orig HDL project, so I choose to use SDK to build a no-OS project.

 

I am using hdl_2017_r1 to build my FPGA project, but the ADI JESD204B Framework has been added in the reference designs.

 

I compare the register definitions in jesd_core.c(..\no-OS-2017_R1\ad9371\sw\platform_xilinx) with the register map in the following link. 

JESD204B Link Receive Peripheral [Analog Devices Wiki] 

They are completely mismatched!!!

So the current jesd_core.c&jesd_core.h is matched with Xilinx JESD IP.

 

Could you provide jesd_core.c&jesd_core.h of ADI JESD IP for me?

 

PS

My previous thread is in the following link:

How to setup AD9371 no-OS successfully 

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