On datasheet of ADL5545 amplifier (on page 5) we find a table that contains the s-parameters of component. Above the table, we read The effects of the test fixture have been deembedded up to the pins of the device.
We are not understand well the meaning of this sentence, but anyway we thought to exploit this thing to optimize the size of evaluation board. Currently, the size are too large and not compliant with size of a receiver for which the component will be used.
The idea is this: we have thought to change the ADL5545's evaluation board layout by reducing (or bending) the length of microstrip between the input (output) capacitor and the input (outpin) pin of amplifier, but we don't know if this change can affect the performance of component. But we have also thought that, after the layout, we can simulate with EM simulator the board using a co-simulation approach, exploiting the deembedded s-parameters provided by the datasheet.
Is it a correct approach? Are there guidelines you suggest us to implement correctly the design?
Many thanks in advance.