This is continuing from a previous question about gapped clocks on AD9557 (ad9557 and gapped clock? ), which was replied by pkern.
I am currently working on a clock recovery circuit that should output a phase locked clock. The circuit includes a comparator and a logic gate that provide a 20 MHz input to the AD9557. When tested with an input that does not miss any data, the output clock of 20 MHz from AD9557 is jitter-free perfectly phase locked with the input on the oscilloscope. But since it has to work with with real time data that might miss a few pulses, I have been testing it with just one missing pulses (gapped clock) periodically. The input is 19.44 MHz and the output expected is a cleaner phase-locked jitter free 19.44 MHz clock. I think because of the gapped clock the indicators weren't showing Phase and Frequency lock in DPLL as well as APLL lock, therefore I increased the DPLL loop bandwidth to 1000 Hz. At this stage, all the indicators are showing lock and there is slight stability in the output, but it has some jitter as well as its not perfectly locking with the input signal when seen on the oscilloscope, though the output is almost around the expected frequency. My questions are:
1. How can I remove the jitter even when the phase and frequency are locked with just one missing pulse (gapped clock) ?
2. If I increase the number of data gaps in the input to AD9557, it doesn't even lock, what do you think I can change to get the output clock less sensitive to gapped clock/missing pulses?
The current AD9557 setup is attached. I have only used wizard to change the input/ouput and loop BW values, all the other values are set to reset default.