I am working on a project for frequency modulation using FPGA and AD9361. The data rate is 20Mbps and require data_clk higher than 80MHz for sampling (at least 4 samples per data) . I found from the data sheet that the LVDS interface allows a data clock up to 240MHz. However, when I design the filter using matlab app, I found that the data clock is up to 61.44MHz. From the register map reference guide, I found that the BBPLL operates from 715 MHz to 1.430 GHz. I like to choose 1200MHz for BBPLL, 600MHz for ADC, 300MHz for DAC, decimate RHB3 by 3 and RX FIR by 2 to obtain a data clock 100MHz, Interpolate THB3 by 3 to obtain a fb clock 100MHz as well. Is it okay to design in this way?