In my application, I'm running a board that's using a Zynq ultrascale and an AD9361. The Zynq is running linux and is using the IIO drivers to communicate to the AD9361 core firmware that we got from the Analog Devices repository. In our application, we're either receiver or transmitting, but not both. When receiving, the data rate onto the FPGA has to be 50 Msamples/s for the downstream logic we feed the data. When transmitting, I don't have a fixed required transmit rate, but the max transmit sample rate we can support is probably around 2 MHz or less. We are trying to make the design such that we don't have to change the sample rates (via IIO commands from the processor) when we switch between receive and transmit. Originally, we tried to use the internal interpolation filters on the AD9361 so that on the Zynq, our receive sample rate = 50 MHz, and the transmit sample rate = 50 MHz / 32. However, it sounds like the AD9361 doesn't support that.
So the next idea is to implement the interpolation on the Zynq fabric itself by placing an interpolation filter somewhere in the path. In the Zynq, the transmit data path is the processor places the data in the DDR, and the AD9361 core pulls the data from the DDR. So we haven't added any custom logic on the transmit side. What I wanted to ask was if anyone had any suggestions on where to place the interpolation filter. My initial thought was to place it in the AD9361 core in between the unpack module and the dac FIFO. But I wanted to see if anyone thought there would be a better place to put the filter.