I'm working with AD9371 eval board and zynq ZC706. I want to add my own FPGA IP into the orig HDL project, so I choose to use SDK to build a no-OS project. Actually, I have done this with AD9361 and Zedboard successfully.
To make it easier for you to solve my problem, I will list my steps.
1.Download hdl-2017_R1 from github and build AD9371 reference design with Cygwin.
2.Download no-OS-2017_R1 from github.
3.Build no-OS projects with SDK .
4.Copy the files in ..\no-OS-2017_R1\ad9371\sw into the src folder of my newly created project
5.Copy the ad9528 and mykonos folder to the src folder of my project, add the paths for the directories are included
6.Generate the profile by using the MATLAB Profile Generator.
8.Add myk.c, myk.h and myk_ad9528init.c to the src folder of my project.
9.Program the FPGA by clicking on Xilinx Tools → Program FPGA.
10.Create a new Run Configuration
11.Click the Run button.
12.Create a new Debug Configuration
13.Click the Debug button.
The information printed on the debug uart port as follows:
WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
device->rx->rxAgcCtrl->agcGainUpdateTime_us out of range in MYKONOS_setupRxAgc()
Maybe I've made some mistakes I didn't realize. Could anyone help me to figure out this issue?
Look forward to a reply as soon as possible!