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How to optimize the ADV7842 output VP clock?

Question asked by WilliamLian Employee on Apr 3, 2018
Latest reply on Apr 4, 2018 by PoornimaSubramani

 

a telepresence customer  is debugging the ADV7842 in the telepresence system, there’s a problem about the  VP clock

 

By the default configure, the VP clock with the glitch as below

 

customer engineers  have tried some ways to eliminate the glitch,

 

  1. change the series resistor value from 0 to 33 to 47ohm, the glitch always be there.
  2. Change the driver ability by reconfigure the 0x14 resister, set the drive ability to the biggest value, could not eliminate the glitch either.

 

Keep the 0x14 value to biggest resister, then change the 0x33 register and observe the VP clock output

 

  1. Configure the IO MAP 0x33 register with the value of 0x3,  the glitch become smaller, but the duty cycle changed, and the design reference documents did not mentioned what’s the meaning when the 0x33 be configured with 0x3, what’s the effect of when the IO MAP 0x33 be configured with 0x3 or 0x43?

 

And why the LLC_DLL_PHASE be changed, the duty cycle will also change?, refer to below waveform

 

 

   Before the 0x19 be configured ( Reg33 be set to 0x43)

 

   After the 0x19 be configured ( Reg33 be set to 0x43, reg19 be adjust from 0x8e to 0x90, the duty cycle changed). What’s the reason?

 

 

 

At last, when REF33=0x43 and REG19=0x90, the glitch become very smaller, customer need ADI help to confirm whether such configure is OK for ADV7842 application?

 

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