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AD9164 - Achieving Deterministic Latency

Question asked by cebrady on Apr 2, 2018
Latest reply on Jul 6, 2018 by deljones

I am trying to obtain deterministic latency between the AD9164 and a Xilinx UltraScale+ FPGA using the Xilinx JESD204B core. I can establish a link between the devices and reliably transfer data, but the latency through the device changes from POR to POR. Note I am running both the DAC and Xilinx Core in Continuous sync mode. The JESD interface is configured as follows.


Data rate: 4.8GHz

Lane rate: 12GHz

PCLK rate: 300MHz

Frame rate: 1.2GHz


L = 8

F = 1

S = 4

I believe that my clock relationships are correct and that I am meeting the Setup/hold requirements for SYSREF but I cant see the clocks right at the part. I can only observe at the PLL generating both DCLK and SYSREF clocks.  Is there anyway to verify using registers inside the part?


To measure the latency through the interface, I have a data generator inside the FPGA that I am using to generate a 300MHz sine wave. Until enabled, the data generator outputs zeros and when enabled generates a 300MHz sine wave. The enable used to start the generator is output with the data and I am using it to measure the delay from the start of data transmission into the JESD transmitter until the data is output from the DAC. I am also reading the the SYSREF_PHASEx  and SYNC_LMFC_STATx registers with each transfer. These are the latencies I am seeing from POR to POR and the SYSREF_PHASE for each:


SYSREF PHASE         Delay

       0xF80                  156.2nS

       0xFC0                  160.0nS

       0xFC0                  136.8nS

       0xF80                   136.8nS

       0xF00                   136.8nS

       0xF80                   136.6nS

       0xF80                   139.8nS

       0xFE0                   137n