While performing digital pulse modulation signal directly to RF using DAC AD9172 EVM, I face some problem, please help.
- Phase reset method at beginning time of each transmitter pulse, ensure phase at the beginning time of each pulse are the same (coherent pulse train). For example, pulse cycle is 10 ms, pulse width is 100us:
- Synchronized reset to sysref: all registers have to set up by this mode (not presented in AD9172 document).
- Reset to an external I/O pin (like AD9161/AD9162 and not presented in AD9172 document)
- Evaluate the impact of sysref jitter and JESD variable latency to phase of signal in DAC channels in synchronization process (in the same IC and between ICs together).