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AD9361 clock rates

Question asked by fishhunterjj on Mar 30, 2018
Latest reply on Apr 1, 2018 by sripad

I am attempting to receive data at 50 MSPS while also being able to transmit data at the lowest possible rate.

 

rx_path_rates value: BBPLL:800000000 ADC:400000000 R2:200000000 R1:100000000 RF:50000000 RXSAMP:50000000
tx_path_rates value: BBPLL:800000000 DAC:200000000 T2:50000000 T1:25000000 TF:12500000 TXSAMP:3125000

 

So far, this is as close as I can get although 1.5625 is possible as well.  Problem is, when I attempt to use these values, I keep getting a few errors to the linux console about " Unhandled case in ad9361_tx_quad_calib line 2663 clkrf 50000000 clktf 12500000", sometimes a tuning error and the transmitted data does not match the waveform that I am pushing.

 

What is the proper way of doing this?

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