Hi, I was looking for xilinx code in ftp name 'FiFO interposer 4-5'
When I tried to run this code(I didn't change the code), but I got an error .
ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock
IOB site. The clock IOB component <I_rclk> is placed at site <G15>. The clock
IO site can use the fast path between the IO and the Clock buffer/GCLK if the
IOB is placed in the master Clock IOB Site. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to
continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition
be corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the
.ucf file to override this clock rule.
< NET "I_rclk" CLOCK_DEDICATED_ROUTE = FALSE; >
But when I see the datasheet of HSC-ADC-EVALCZ, rclk pin was G15.
Hope I can get an answer quickly.