I've been trying to change the device clock from 122.88 MHz to 125 MHz. Since I have to work with a 10 MHz reference clock. I changed the 122.88 MHz VCXO with 100 MHz VCXO (Crystek Corp.) to get 125 MHz device clock.
I changed the PLL2 divider parameters like M1 = 4 N2 = 35 chDIV = 7 in profile generated by the filter wizard but it did not work. Could you please help me on how I changed the device clock? Should I change the parameters given in the source codes or should I use the filter wizard?