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The DATA LATENCY (PIPELINE DELAY) about AD9910 and the use of Matched latency enabled

Question asked by itmy on Mar 27, 2018
Latest reply on Jul 18, 2018 by deljones

The datasheet about AD9910  declares specific value of the Data Latency to DAC output in different modulation modes.


Is this Data Latenct referring to the delay of DDS analog output after IO_UPDATE pulled up? or  the time needed to arrive at the valid register from each port buffer(in this case ,does FTW,POW and ASF to DDS output synchronize? )


The second question:

Can it be considered that the amplitude, phase and frequency synchronously DDS output in the case of the Matched latency enabled?  Specifically,I configure a sine or cosine wave with certain frequency and use RAM for phase modulation.Can I think that the two mode are simultaneous enabled and configured at the same time(In order to have a definite initial phase)?