Now we are evaluating ADSP-21489+AD1939 solution based on the EVB board, we want to learn,
can AD1939 get 8k sample rate if if use DSP internal PCG and SRC woking with TDM mode? Sorry we fail to find answer in the datasheet.
I am the support person for the AD1939. So I can help you with that part of this but someone else will have to help you with how to make the DSP send out the proper frequencies.
The codec can operate at 8kHz fs but the PLL is not capable of operating at that low of a frequency. So you must direct clock the part by bypassing the PLL and clocking the ADC and the DAC directly from the MCLKI pin. There are register settings to do this.
Then the masterclock MUST be 512 x fs when direct clocking. So the master clock must be 4.096MHz to run at 8kHz. The bit clock and the LRCLK must be synchronous to the master clock. In other words they must be divided down from the master clock so that there are exactly the correct number of master clock cycles per frame. (512)
Thank you for the support.
We will also wait for the advice from DSP Specialist.
suppose i should @Jithul_Janardhanan
Still this EVAL-SHAUDIO-EZEXT issue, now if i use DSP SRC(asynchronous sample rate converter), the output of AD1939 delay 15ms, i've already checked the time sequence of DSP SRC and they just us level, so we wonder whether it is caused by AD1939, can you kindly help to advice.
As DaveThib stated correctly, in order to use the AD193x at lower than the standard frequency window of 32 kHz – 192 kHz, an MCLK of 512 x Fs must be provided at the MCLKI port. In addition, the ADC and DAC clock source bitfields must be set to MCLK, instead of the default PLL. So you may have to use an oscillator of 4.096MHz than the default 12.288MHz (U12) on the Ez-board.
Apologies for the delay. Yes, the PCG can be used to generate 8KHz frame sync output. Using SRU routing it can be routed to any of the DAI pins and can be probed.
Also, you would find the following discussion https://ez.analog.com/message/38539?commentID=38539#comment-38539 to be useful.
Thank you so much for your attention and advice, we will study it carefully.
Have you read the AD1896 datasheet? It is a great reference as to how the ASRC functions. On page 21 there is a formula for the group delay of the filter. I am fairly certain that the one built into the SHARC is using the higher clock rate so the first set of formulas should be the ones to use. So with that assumption I would calculate the group delay but I do not know the starting sample rate. The fs-in. I know you want to use the fs-out = 8kHz but you never mentioned in your posts what you are starting with?
The formula is (16/fsin) + (32/fsin) * (fsin/fsout) in seconds if fs-out < fs-in which is assume to be the case.
Then realize that running at 8kHz fs everything is slower. Simply transmitting a frame of data will take 0.125ms. Typically it takes one sample period to transmit the data in serial fashion, then one sample period to clock it into the DAC once it is received. Then the digital filters in the DAC are running slower as well. The group delay of the digital filters for the DAC will be around 25/fs. so 25/8000 = 3.125 ms inside of the DAC.
I do not know where you are measuring the 15 ms from? Is this from an analog input signal? Because then you need to add the group delay of the ADC filters. That is almost 3ms. Then all the delays from clocking in the data and re-clocking and buffering the data and I think you might get up to 15ms before long. If you are using some IIR filters in the DSP processing then that will also cause a group delay. As you see it becomes a little tricky tracking down all the delays.
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