I'm using AD9364 in custom board with microsemi IGLOO2 FPGA with NO-OS driver. I'm trying to test the BIST tone at Tx port and I run the main.c of driver. The order is listed below,
ad9361_init(&ad9361_phy, &default_init_param , (void*)handle);
temp = ad9361_ensm_get_state(ad9361_phy); // to check out whether the ENSM is still in proper state or not
ad9361_set_tx_lo_freq ( ad9361_phy , 300000000);
ad9361_bist_tone (ad9361_phy ,1,0,0,0) // injecting at Tx port, Full scale with Fs/32
Since we are using the default init structure, the transceiver is in FDD mode(even after running the init())
But I'm not getting the BIST tone, instead I'm just getting a LO frequency only at the output.
My doubt are as follows:
1) Do transceiver needs FPGA for BIST tone generation(as of now FPGA is not active in our board)
2) Clocks looks spurious, Is this spurious affecting the BIST tone generation?
3) Do we need to run the set_tx/rx_fir_config before running BIST tone?
4) I'm seeing LO tone of -14dBm at 0dB Tx attenuation. What is causing the LO leakage of this much amplitude?