# Problems with conversion time of AD7124-4

Question asked by jay_hj on Mar 26, 2018
Latest reply on Apr 5, 2018 by JellenieR

Above picture is a brief schematic of the configuration I have. This is only an emulation of the real circuit since the real circuit wouldn't be purely resistive. For my current application, I must have a current source that switches its polarity and read the voltage v2-v1 after 1ms of the switch. In my current setup, for the first cycle I have a current source in AIN0 and VBIAS at AIN3 and for the second cycle, I have a current source at AIN3 and a VBIAS at AIN0. I read V2-V1 in a bipolar configuration with single conversion mode after 1ms of setting the excitation current. The 1ms is basically the time for the capacitance to charge up in the real circuit. My idea was to use a filter setting that would provide 1ms of conversion time. With SINC4 and FS =4, the calculations gave me a settling time of 1ms, but I ended up getting junk value when I wait for 1ms ( I tried giving a delay up to 8ms too) before reading the value. I know this because currently, v2-v1 has a 4k resistor and the v2-v1 measurement should give approx +0.4v for 100uA excitation current in the first cycle and -0.4v in the second cycle. When I use a delay of greater than 10ms, I seem to get the right value.

This is my program flow.

1. reset ADC, setup channel, set up configuration

2. Set filter with SPS=25, FS = 4

3. Set offset register

while(1){

// First cycle

4. Set 100uA excitation current AIN0, VBIAS on AIN3

5. delay 1ms, for current to stabilize

6. Write to ADC_CONTROL (internal reference, single conversion mode, full power mode)

7. Wait for 1ms // waiting for conversion to be ready

8. Poll status register to confirm if the data is ready

10. Set current to zero

//Second cycle

11. Set 100uA excitation current AIN3, VBIAS on AIN0

12. delay 1ms, for current to stabilize

13. Write to ADC_CONTROL (internal reference, single conversion mode, full power mode)

14. Wait for 1ms // waiting for conversion to be ready

15. Poll status register to confirm if the data is ready