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ADV7441A: SDP output delay

Question asked by Vid123 on Dec 6, 2011
Latest reply on Dec 8, 2011 by Vid123

Hi,

 

I have couple questions about the delay of the digital output compare to its analog input in SDP process

 

1) What is the delay (in clk cycles, H-lines, or time unit) for SDP, and is it changable?   By observation I see it's about 180 micro second for a NTSC video - is this correct ?

 

2) In SDP can we output the CS (composite sync) on the HS/CS (pin 17) ?

 

 

Thanks,

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