We are using the AD9371 transceiver in a custom board design. I am trying to use the Analog Devices HDL code as a starting point, however I am struggling to understand the design that is generated. I have built the AXI_AD9371 core and this core makes sense, however when I look at the HDL generated for the TX and RX JESD204B link layers I cannot figure out how this connects to the AXI_AD9371 core.
I issue the a make all command in the ../hdl/projects/adrv9371x/zc706/ directory.
I also cannot locate the HDL that performs the framing and deframing as show in Figure 7 of the AD9371 User Guide. Eventually we need to get to four data lanes as this is what is in the AD9371 JESD204 interface. Thanks.