After searching for many hours why the JESD204 link was down (kept in CSG phase), I found that jesd_core.c might be improved. The following line
tx_xcvr.lane_rate_khz = myk_dev->tx->txProfile->iqRate_kHz * 20;
does not take into account the number of active lanes (neither the deframer->M), although there are used in the API in mykonos.c.
I have modified jesd_core.c (rx_xcvr.lane_rate_khz, tx_xcvr.lane_rate_khz, rx_os_xcvr.lane_rate_khz), and I have now better results.
I still have some troubles depending of the choice of active lanes. I am not sure the FPGA is correctly configured to use only active lanes, and to send/receive data on the correct lanes.
no-OS-2017_R1, hdl-2017_r1, Vivdao 2016.4, SDK 2017.4,
Xilinx ZC706 kit, ADRV9371