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the SPI control of  the AD7768-4

Question asked by liu123 on Mar 26, 2018
Latest reply on Mar 29, 2018 by jcolao

I meet the three questions as follows:


1.I can't understand the content of SPI CONTROL FUNCTIONALITY in page 50 

that After any change to these configuration register settings, the user must provide a sync signal to the AD7768/AD7768-4 through either the SPI_SYNC command,

Could you tell me the detailed operation that how to use SPI_SYNC command?


2. about the  The minimum DCLK rate,I found the Format0 of the Evaluation board of AD7768-4 is 0,so the samples data is output by four of DOUTx pins.the minimum DCLK rate should be 8.192Mhz,but I found that the actual DCLK of Evaluation board is 32Mhz.

Could you give me some advice about this question?


3.About the operation step of SPI control of the AD7768-4,my understand is as follows


   1) the FPGA writes the configuration register settings into the AD7768-4 by spi.

   2) the FPGA writes SPI_SYNC commands into the AD7768-4 by spi,the data can be output.

   3)the FPGA reads data from the AD7768-4 by DCLK and DOUTx.

Is my understand right?