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Setup of AD9144

Question asked by yzzhsx123 on Mar 22, 2018
Latest reply on Mar 27, 2018 by yzzhsx123

Hello Everyone, 

I am trying to connect the AD-FMC-DAQ2 to KCU105 FPGA, and reccently I met the problem with setting up the AD9144. I have used the following code to do the basic setup, then I give the digital signal and get the waveform from the oscilloscope, from which the frequency is 250MHz. Now I want to make the change so I can get the different frequency,and I have several questions about the setup code, which is referred from : EngineerZone: Message List 

 

1. The input reference clock sourced from input port is 1GHz, I am confused about the DAC CLK, does it use the DAC PLL or directly use the input reference CLK?

2. In the section of required device configurations, why set (0x1c4, 0x73) since I found it should be set 0x7e in AD9144 manual.

3. What does (0x291, 0x49) mean since I didn't find it in the manual. 

 

int wr_reg_spi (int dev, unsigned long offset, unsigned long data)
{
//ioctl ( 3, 0xffff & (~(0x1 << (dev-1))));
*((uint32_t *) map_base + (0x0002) ) = 0xffff & (~(0x1 << (dev-1)));
usleep(1000);
//printf("wr_reg:%X\n", 0xffff & (~(0x1 << (dev-1))));
//ioctl ( 4, ((offset<<8)+data)<<8);
*((uint32_t *) map_base + (0x0000) ) = ((offset<<8)+data);
*((uint32_t *) map_base + (0x0001) ) = 0x1;

usleep(1000);
//printf("wr_reg:%X\n",((offset<<8)+data)<<8);
//ioctl ( 3, 0xffff);
*((uint32_t *) map_base + (0x0002) ) = 0xffff ;
usleep(1000);
//printf("wr_reg:%X\n",0xffff);

return 0;

int cfg_DAC()
{
wr_reg_spi(1,0x000, 0x81); // reset
wr_reg_spi(1,0x000, 0x00); // reset


wr_reg_spi(1,0x011, 0x00); // dacs - power up everything
wr_reg_spi(1,0x080, 0x00); // clocks - power up everything
wr_reg_spi(1,0x081, 0x00); // sysref - power up/falling edge

// required device configurations

wr_reg_spi(1,0x12d, 0x8b); // data-path
wr_reg_spi(1,0x146, 0x01); // data-path
wr_reg_spi(1,0x520, 0x1c); // sysref-armed

wr_reg_spi(1,0x040, 0x00); // current
wr_reg_spi(1,0x041, 0x02); //
wr_reg_spi(1,0x042, 0x00); //
wr_reg_spi(1,0x043, 0x02); //

 

// wr_reg_spi(1,0x146, 0x00); //
// wr_reg_spi(1,0x520, 0x1e); //
// wr_reg_spi(1,0x521, 0x00); //
// wr_reg_spi(1,0x522, 0x00); //
// wr_reg_spi(1,0x523, 0x00); //
// wr_reg_spi(1,0x524, 0x00); //

wr_reg_spi(1,0x2a4, 0xff); // clock
wr_reg_spi(1,0x1c4, 0x73); // dac-pll
wr_reg_spi(1,0x291, 0x49); // serde-pll
wr_reg_spi(1,0x29c, 0x24); // serde-pll
wr_reg_spi(1,0x29f, 0x73); // serde-pll
wr_reg_spi(1,0x232, 0xff); // jesd
wr_reg_spi(1,0x333, 0x01); // jesd

// digital data path

wr_reg_spi(1,0x112, 0x00); // 2x interpolation
wr_reg_spi(1,0x110, 0x00); // 2's complement
wr_reg_spi(1,0x111, 0xa0); // fdac/4 modulation
wr_reg_spi(1,0x13c, 0xff); // I gain
wr_reg_spi(1,0x13d, 0x07); // I gain
wr_reg_spi(1,0x13e, 0xff); // Q gain
wr_reg_spi(1,0x13f, 0x07); // Q gain

 


// transport layer

wr_reg_spi(1,0x200, 0x00); // phy - power up
wr_reg_spi(1,0x201, 0x00); // phy - power up
wr_reg_spi(1,0x300, 0x01); // single link - link 0
wr_reg_spi(1,0x450, 0x00); // device id (0x400)
wr_reg_spi(1,0x451, 0x00); // bank id (0x401)
wr_reg_spi(1,0x452, 0x04); // lane-id (0x402)
wr_reg_spi(1,0x453, 0x83); // descrambling, 4 lanes
wr_reg_spi(1,0x454, 0x00); // octects per frame per lane (1)
wr_reg_spi(1,0x455, 0x1f); // mult-frame - framecount (32)
wr_reg_spi(1,0x456, 0x01); // no-of-converters (2)
wr_reg_spi(1,0x457, 0x0f); // no CS bits, 16bit dac
wr_reg_spi(1,0x458, 0x2f); // subclass 1, 16bits per sample
wr_reg_spi(1,0x459, 0x20); // jesd204b, 1 samples per converter per device
wr_reg_spi(1,0x45a, 0x0a); // HD mode, no CS bits
wr_reg_spi(1,0x45d, 0x49); // check-sum of 0x450 to 0x45c
wr_reg_spi(1,0x46c, 0x0f); // enable deskew for all lanes
wr_reg_spi(1,0x03a, 0xc1); // sysref-armed
wr_reg_spi(1,0x476, 0x01); // frame - bytecount (1)
wr_reg_spi(1,0x47d, 0x0f); // enable all lanes

// physical layer

wr_reg_spi(1,0x2aa, 0xb7); // jesd termination
wr_reg_spi(1,0x2ab, 0x87); // jesd termination
wr_reg_spi(1,0x2b1, 0xb7); // jesd termination
wr_reg_spi(1,0x2b2, 0x87); // jesd termination
wr_reg_spi(1,0x2a7, 0x01); // input termination calibration
wr_reg_spi(1,0x2ae, 0x01); // input termination calibration
wr_reg_spi(1,0x314, 0x01); // pclk == qbd master clock
wr_reg_spi(1,0x230, 0x28); // cdr mode - halfrate, no division
wr_reg_spi(1,0x206, 0x00); // cdr reset
wr_reg_spi(1,0x206, 0x01); // cdr reset
wr_reg_spi(1,0x289, 0x04); // data-rate == 10Gbps
wr_reg_spi(1,0x280, 0x01); // enable serdes pll
wr_reg_spi(1,0x280, 0x05); // enable serdes calibration


wr_reg_spi(1,0x268, 0x62); // equalizer

// cross-bar

wr_reg_spi(1,0x308,0x11); // lane selects
wr_reg_spi(1,0x309,0x03); // lane selects

// data link layer

wr_reg_spi(1,0x301, 0x01); // subclass-1
wr_reg_spi(1,0x304, 0x00); // lmfc delay
wr_reg_spi(1,0x305, 0x00); // lmfc delay
wr_reg_spi(1,0x306, 0x0a); // receive buffer delay
wr_reg_spi(1,0x307, 0x0a); // receive buffer delay
wr_reg_spi(1,0x03a, 0x01); // sync-oneshot mode
wr_reg_spi(1,0x03a, 0x81); // sync-enable
wr_reg_spi(1,0x03a, 0xc1); // sysref-armed
wr_reg_spi(1,0x300, 0x01); // enable link

// dac calibration

wr_reg_spi(1,0x0e7, 0x38); // set calibration clock to 1m
wr_reg_spi(1,0x0ed, 0xa6); // use isb reference of 38 to set cal
wr_reg_spi(1,0x0e8, 0x03); // cal 2 dacs at once
wr_reg_spi(1,0x0e9, 0x01); // single cal enable
wr_reg_spi(1,0x0e9, 0x03); // single cal start


wr_reg_spi(1,0x0e7, 0x30); // turn off cal clock

 

return 0;
}

 

I really hope anyone who has the relevant experience can help me with it, thank you soooo much!!

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