Hi there everyone,
in the past we already implemented a system with an FPGA, an ADC and a DAC using JESD subclass one. Last time we had a clock generator which also provided the sysref signal (which to my understanding is inevitable) and we knew the trace length to the various parts and delayed the various signals accordingly.
So basically my question is: Do I have to delay the various signals according to their trace length so that the sysref signal reaches all relevant chips at the same time? Or is it only relevant to be always the same?
Thanks in advance,