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JESD204B Rx core from AD: problem with lane alignment

Question asked by kvantumnuly on Mar 22, 2018
Latest reply on Mar 22, 2018 by AdrianC

Hi all,

I am using IP core from JESD204B Link Receive Peripheral [Analog Devices Wiki]  ( static configuration without AXI)

My design meets with requirements on page above. 

K=4

F=8

lanes=8

Scrambler on

For PHY layer I use JESD204 PHY IP core (not from AD). It seems, that there is a problem with lane alignment. It should not be a problem with ADC (I also try it with TI ADC with same result).

There is a output from ILA, ramp function:

E.g. Rx vector per one clock:

77767574 79787776 79787776 78777675 79787776 77767574 79787776 79787776

What may cause this problem?

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