I am using IP core from JESD204B Link Receive Peripheral [Analog Devices Wiki] ( static configuration without AXI)
My design meets with requirements on page above.
For PHY layer I use JESD204 PHY IP core (not from AD). It seems, that there is a problem with lane alignment. It should not be a problem with ADC (I also try it with TI ADC with same result).
There is a output from ILA, ramp function:
E.g. Rx vector per one clock:
77767574 79787776 79787776 78777675 79787776 77767574 79787776 79787776
What may cause this problem?