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ADAU1462/1466 data sheet, several issues.

Question asked by Euglena on Mar 22, 2018

I am referring the latest ADAU1462/1466 data sheet Rev.C.

Please let me confirm below. If there are document anomalies, could you modify them in future?

 

1. Digital Input voltage, no noise margin

Is following specification correct?

Page 7 Table 4.

DIGITAL INPUT / Input Voltage

High Level (VIH) Min. 1.71V

Low Leve (VIL) Max.1.71V

On the ADAU145x, there is a similar thread.

 https://ez.analog.com/thread/89303-adau1452s-electrical-characteristic-of-iovdd-digital-input-voltage

 

2.SPI Slave port timing

Depending on the page, the CPHL and CPHA settings are different. Which is correct information?

a). CHOL=0 CPHA=0, mode 0

Page 14 Table 13, Figure 8. SPI Slave Port Timing Specifications

Page 43 Figure 36. Clock Polarity and Phase for SPI Slave Port

b). CHOL=1 CPHA=1, mode 3

Page 42 SPI Slave Port

  The format for the SPI communications slave port is commonly known as SPI Mode 3,

  where clock polarity (CPOL) = 1 and clock phase (CPHA) = 1 (see Figure 36).

  The base value of the clock is 1.

  Data is captured on the rising edge of the clock, and data is propagated on the falling edge.

Page 44

  Figure 37. SPI Slave Write Clocking (Burst Write Mode, N Bytes)

  Figure 38. SPI Slave Read Clocking (Single Word Mode, Two Bytes)

  Figure 39. SPI Slave Read Clocking (Burst Read Mode, N Bytes)

 

3. Control Register description

On page 92 - 97 Table 59. Control Register Summary,

the "0xF899 SECONDPAGE_ENABLE" and "0xF890 SOFT_RESET", the order of these registers is reversed.

Around page 196, there are not descriptions about the "0xF899 SECONDPAGE_ENABLE".

 

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