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Changing Sysref generation for different clock rate

Question asked by htorke on Mar 21, 2018
Latest reply on Apr 13, 2018 by sripad

We have 2 ADRV9371 boards, one of which is in the default configuration to use a 30.72MHz clock, and another which is modified to instead use a 100MHz clock. The former succeeds in the initialization using the baremetal API, where as the latter fails the multichip sync step, returning mcsStatus of 0. I am using the following sysref settings for both:

 

 

static ad9528pll1Settings_t clockPll1Settings =

{

0,

1,

0,

0,

1,

0,

100000000,

3,

1,

1

};

 

static ad9528pll2Settings_t clockPll2Settings =

{

3,

48,

144

};

 

static ad9528outputSettings_t clockOutputSettings =

{

53237,

{0,0,0,2,0,0,0,0,0,0,0,0,2,0},

{0,0,0,0,0,0,0,0,0,0,0,0,0,0},

{0,0,0,0,0,0,0,0,0,0,0,0,0,0},

{0,0,0,0,0,0,0,0,0,0,0,0,0,0},

{7,7,7,7,7,7,7,7,7,7,7,7,7,7},

{150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000, 150000000}

};

 

static ad9528sysrefSettings_t clockSysrefSettings =

{

0,//Request Method

2,//Source

0,//Pin Edge Mode

0,//Pin Buffer Mode

1,//Pattern Mode

0,//Nshot Mode

512//Sysref Divide

};

 

 

but the behavior is different. Do I need to generate the sysref pulse differently with a different refclk frequency?

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