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AD9375 LO PLL and QEC settling time

Question asked by sugu89 on Mar 21, 2018
Latest reply on Apr 27, 2018 by PVALAVAN



We are planning to use AD9375 for our frequency hopping application where we may requires minimum 2000 Hops/sec.

Where we require Receiver and Transmitter LO frequency settling time is <5uS.

Since the internal Architecture is based on PLL based, We don't think the PLL settling time is better than 50uS which may not meet our application requirement.

So we are planning to use our external LO signal to AD9375 with fast switching Synthesizer.


1) What is the internal PLL settling time?


2) During frequency hopping what will be receiver and Transmitter QEC settling  time? This is required for us to finalize the AD9375 for our application requirement. If QEC settling time is more than 10uS then we may not use QEC for our application. In this case of QEC disabled what will be image rejection specification of AD9375?


3) How to switch the internal LO to external LO what is the switching time?


Sugumar K