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ad9523-1 PLL2 loop bandwidth design

Question asked by luca.banchi on Mar 21, 2018
Latest reply on Mar 26, 2018 by luca.banchi

Dear support,

Sorry for duplicate!


I use the AD9523-1 as clock distributor in my design. In the AD9523-1 only PLL2 is adopted, i.e. the PLL1 is by-passed, as described in the datasheet pag. 23.

My system reference at 100MHz shows detrimental spurs at 150kHz offset (and harmonics) from the carrier due to a not well isolated switching regulator. So, I want to decrease as low as possible the bandwidth of the PLL2 loop in order to reject as much as possible those spurs.

I tried a design with 1kHz bandwidht. By using the ADIsimCLK software, I got the following values:
Cpole1 = 48pF

Rzero = 3.25kOhm

Rpole2 = 900Ohm.

Czero = 820nF.


Therefore, I set the registere 0x0F5 at 0F (00 000 111) and I placed a 1uF capacitor in between LF2_EXT_CAP (pin11) and LDO_VCO (pin12), and a capacitor of  1uF from  LDO_VCO (pin12) to GND.

By looking at the spectrum, no real benefit appeared: the spurious are still present and not attenuated in any way.

For my understanding in PLL, the loop should redude the components outside the loop bandwidth...

Could you please help me in understanding the effect of PLL2 loop filter on the reference signal?

How can I reduce those 150kHz reference spurs?


Thank you for your help.