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using PCG's to drive AD1939 ADC and DAC as SLAVE's

Question asked by johnmurray on Dec 5, 2011
Latest reply on Jan 31, 2012 by Harshit.Gaharwar

Hi

 

I started working on a project where we had the ADSP21479 conencted to other external Codec Evaluation boards.

The problem is that sometimes I would get audio comming through, and other times I would not, basically sometimes the SP1 Interrupt would get called and other times it would not, hence no audio passing through.

 

I am not sure if there is a problem with the alignment or syncronisation of the clock signals I am generating or if its a problem with the wiring between the 3 evaluation boards.

 

So, I am now trying to replicate the same project but on the ADSP21479 Evaluation board using the onboard AD1939 converters.

 

I am running I2S, Block Based and want to generate my clock signals using the PCG’s.

I have added a Jumper to JP5 which connects the Audio OSC 24 MHZ to DAI Pin 17, and this is used as my input clock.

 

I am creating a  6.144 MHz clock, a 96 kHz clock and the master clock is 24 MHz

 

I have switched the Enable switches #5 and #6 on the SW2 Switch, this should enable the DAI_P13 and DAI_P14 clock signals to be routed to the AD1939 DBCLK and DLRCLK.

 

I have changed the AD1939 to be a slave for both DAC and ADC

 

(AD1939_ADDR), DACCTRL1, DAC_BCLK_SRC_PIN| DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE  | DAC_CHANNELS_2 | DAC_LATCH_MID, //Ddebug

            (AD1939_ADDR), DACCTRL1, DAC_BCLK_SRC_PIN| DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE  | DAC_CHANNELS_2 | DAC_LATCH_MID, //Ddebug

            (AD1939_ADDR), DACCTRL2, DAC_WIDTH_24,

         

            (AD1939_ADDR), ADCCTRL0, ADC_SR_96K,

   

            (AD1939_ADDR), ADCCTRL1, ADC_LATCH_MID | ADC_FMT_I2S | ADC_BCLK_DLY_1 | ADC_WIDTH_24,          

         

            (AD1939_ADDR), ADCCTRL2, ADC_BCLK_SRC_PIN | ADC_BCLK_SLAVE | ADC_CHANNELS_2 | ADC_LRCLK_SLAVE | ADC_LRCLK_FMT_50_50|ADC_LRCLK_POL_NORM|ADC_BCLK_POL_NORM, // NDdebug 

            (AD1939_ADDR), ADCCTRL2, ADC_BCLK_SRC_PIN | ADC_BCLK_SLAVE | ADC_CHANNELS_2 | ADC_LRCLK_SLAVE | ADC_LRCLK_FMT_50_50|ADC_LRCLK_POL_NORM|ADC_BCLK_POL_NORM, // NDdebug                

            (AD1939_ADDR), DACVOL_L1, DACVOL_MAX,

 

Unfortunatly I can't even get the project to work with the AD1939 converters so am wondering if I am seting them up or the PCG's correctly.

 

Thanks

John

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