We have a Xilinx ZC706 and an ADRV9371 kit. We are able to configure it using the Transceiver Evaluation Software, and also to "Create C Script" that can also configure the kit (no-OS). The deframer status is normally 0x68, which is fine.
We have tried to change the deframer configuration (just to see if it has some effect):
deserializerLanesEnabled (to activate other lanes),
deserializerLaneCrossbar (to permute the lanes),
enableManualLaneXbar set to 1.
Tghe following three points are strange to us:
- We could have a deframer status other than 0x68 only if we change the configuration after power up. It seems to me that the MYKONOS_readDeframerStatus reads from SPI the current status, but once the status is 0x68, it does not change any more even if we run the whole C Script to reconfigure the transceiver.
- Even when the deframer status is bad (0x21), the result on the spectrum analyser is the same as before. We generate a continuous wave with a single tone.
- I can see more or less that the deframer status is used to configure the AD9371, but I did not found where it is used to configure the FPGA of the ZC706. The FPGA must know which lanes to use...
Could you explain that?
hdl-2017_r1, Vivdao 2016.4, SDK 2017.4