caugusta

Jitter Attenuator Questions

Discussion created by caugusta Employee on Mar 19, 2018
Latest reply on Mar 23, 2018 by kpeker

Team, customer has the following questions. 

  • 1) I need a recommendation for an IC to clean up a differential-pair clock signal which has a frequency around 250MHz, having SSC behavior (0..-5000PPM frequency modulation, 30..33KHz modulation frequency, ideally triangular modulation).
  • The high-frequency jitter needs to be eliminated (max jitter output to be on the order of <<10ps pp), while the low-frequency SSC behavior needs to be completely preserved, including all nonideal/nonlinear signal (frequency modulation) behaviors.
  • If all signal artifacts up to at least 1MHz can be preserved that would probably suffice, with all nonideal behavior above that frequency, including the jitter as mentioned, removed.
  • The IC should ideally be able to produce two differential-pair output clones of the cleaned-up clock signal. The IC should also ideally be able to handle more than one input signal at a time, e.g., be able to handle cleaning up to four input signals.
  • The HMC7044 was suggested, PLL2 needed to be used per the loop bandwidth required.
  • The output jitter is key, but only over the first ten or so output cycles (relative to any given earlier output clock edge).  How can the datasheet phase noise and jitter specs be translated into some metric which will indicate what the max peak-to-peak near-in-time time-domain jitter would be?
  • 2) Given that an appropriate clock-cleaning IC is employed, a related requirement is to make a very accurate measurement of the peak frequency achieved during the SSC modulation period.
  • As indicated above, the peak clock frequency is about 250MHz, and while the frequency is known up front to an accuracy of about +/-300PPM, the frequency needs to be measured more accurately to within +/-50PPM or better. 
  • The accurate frequency measurement needs to be performed in real time over no more than about 40 clock cycles (150ns or so).  Repeated passes, with repeated measurements of the SSC peak frequency being made, could be done if necessary, up to a max of about 250 passes.
  • Bench-top test equipment could be used as a last resort, however it is preferred to include the needed measurement circuitry as part of a larger PCB design.
  • 3) Further related to all of this is the AD9577, whose datasheet shows in Fig.29 a plot of output frequency variation with time, with the plot having an apparent resolution/accuracy of better than 1:10000 (100PPM).
  • The plot's frequency extremes are seen to last much shorter than 1us.  How can the frequencies of the short-duration peaks be determined to such accuracy?  What test equipment is used to produce such a plot?
  • And, is the plot produced in real time, or is the plot the result of many repeated passes, with exactly-similar output signal behavior expected/required on each pass, in order to build up a nicely-averaged view of the signal behavior over time?

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