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ADF5355 Reg 10 ADC_CLK_DIV formula error? 

Question asked by gtxlt on Mar 18, 2018

On datasheet Rev. D | Page 32 of 38 there seems to be an error in the formula to calculate the ADC clock divider. Can you please clarify?  In the example Fpfd / ADC_CLK_DIV = 61.44 MHz / 154 = about 400 kHz (not 100 kHz)???

For reference from the datasheet:

"Choose the value such that ADC_CLK_DIV= Ceiling(((fPFD/100,000)− 2)/4)where Ceiling() rounds up to the nearest integer.  For example, for fPFD= 61.44 MHz, set ALC_CLK_DIV= 154 so that the ADC clock frequency is 99.417 kHz."

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