On datasheet Rev. D | Page 32 of 38 there seems to be an error in the formula to calculate the ADC clock divider. Can you please clarify? In the example Fpfd / ADC_CLK_DIV = 61.44 MHz / 154 = about 400 kHz (not 100 kHz)???

For reference from the datasheet:

"Choose the value such that ADC_CLK_DIV= Ceiling(((fPFD/100,000)− 2)/4)where Ceiling() rounds up to the nearest integer. For example, for fPFD= 61.44 MHz, set ALC_CLK_DIV= 154 so that the ADC clock frequency is 99.417 kHz."

Hi,

The formula is correct. The previous sentence (

The ADC uses a clock that is equal to the output of the R counter (or the PFD frequency) divided by ADC_CLK_DIV.) seems to be confusing.ADC CLK can be calculated using the inverse of the given formula. This can be seen explicitly in the GUI:

Regards,

Kazim