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ADV7181D troubles with composite synchro

Question asked by acid on Mar 17, 2018
Latest reply on Mar 19, 2018 by PoornimaSubramani

Hi. I'm using ADV7181D with RGB signal (PAL-like - 50Hz/15.625kHz). It works quite good with separated hsync and vsync signals, but when I tried to connect csync instead it has problems (loosing horizontal synchronisation around vertical sync).

When I mix csync with green (in a stupid way - just using simple resistor) it works (of course green is a little off - because of the way I mixed those signals) - my green input is connected to one AIN and to SOG (using proper capacitors of course).

I also tried to send csync (via different voltage dividers to decrease signal level) to SOY (and tell ADV to use SOY instead of SOG) - no sync at all.

The funny thing is that csync connected to HS_IN/CS_IN (pin 56) is detected as csync (reading 0xB5 gives two lowest bits set to 2'b10), but it is loosing h-synchro around vsync - around vsync in proper csync signal there are half-line pulses - it looks like ADV tried to use them as full-line hsync pulses which is not correct. Lines around vsync have different pixel count than other lines. Output hsync pulses "are moving" (different and rather strange delays between pulses).

I've also tried to force using CS on HS_IN (set bits 4 and 3 in 0x85 to 2'b10) - nothing has changed.

 

What is the best (preferred) way to connect csync signal to ADV7181D (or maybe there are some bits in I2C registers I should set)? 

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