I'm running an AD9689-2600. The datasheet says that the sample clock divider is 2. So for a 2.56 GHz sample clock like in the datasheet the clock input would need to be 5.12 GHz. Seems like the ADC is getting setup correctly however, the FFT still says the sample clock is 5.12 GHz not the 2.56 GHz.
Will post a screen shot.