We are trying to understand how clocks work in DAQ2.
Following output clocks are listed on page AD-FMCDAQ2-EBZ Clocking [Analog Devices Wiki]
|PLL2 VCO||3000 MHz||Tuning range of 2940 MHz to 3100 MHz|
|Master clock||1000 MHz, 750 MHz, 600 MHz||PLL2 VCO divided by 3, 4 or 5|
|ADC converter clock||≥ 312.5 MHz, ≤ 1000 MHz, Master clock / NADC|
|ADC SYSREF clock||ADC converter clock / (NADC_SYSREF * 32)|
|DAC converter clock||≥ 200 MHz, ≤ 1000 MHz, Master clock / NDAC|
|DAC SYSREF clock||DAC converter clock / (NDAC_SYSREF * 32)|
|ADC JESD204 lane rate||ADC converter clock / ADC decimation factor * 10|
|DAC JESD204 lane rate||DAC converter clock / DAC interpolation factor * 10|
Regarding ADC converter clock and DAC converter clock, their min values are 312.5mhz and 200mhz respectively. I am aware that both min rates are dependant on jesd rate.
My question is that, are these min values 312.5mhz and 200mhz correctly?