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output clocks of DAQ2

Question asked by James12345 on Mar 16, 2018
Latest reply on Jul 17, 2018 by deljones

Hi there,

 

We are trying to understand how clocks work in  DAQ2.

 

Following output clocks are listed on page AD-FMCDAQ2-EBZ Clocking [Analog Devices Wiki] 

ClockFrequency rangeComments
PLL2 VCO3000 MHzTuning range of 2940 MHz to 3100 MHz
Master clock1000 MHz, 750 MHz, 600 MHzPLL2 VCO divided by 3, 4 or 5
ADC converter clock≥ 312.5 MHz, ≤ 1000 MHz, Master clock / NADC
ADC SYSREF clockADC converter clock / (NADC_SYSREF * 32)
DAC converter clock≥ 200 MHz, ≤ 1000 MHz, Master clock / NDAC
DAC SYSREF clockDAC converter clock / (NDAC_SYSREF * 32)
ADC JESD204 lane rateADC converter clock / ADC decimation factor * 10
DAC JESD204 lane rateDAC converter clock / DAC interpolation factor * 10

 

Regarding ADC converter clock and DAC converter clock, their min values are 312.5mhz and 200mhz respectively. I am aware that both min rates are dependant on jesd rate. 

My question is that, are these min values  312.5mhz and 200mhz correctly?

 

Cheers,

James

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