I use the ADI DMAC for playing out chirps in cyclic mode through the FIFO destination interface.
Now i would like to enable RX capturing with ADI DMAC fifo interface only on a specific range in the chirp. For this i am running a counter with enable connected to fifo_rd_valid. Based on counter value I assign fifo_wr_en to enable capturing DDC samples with 8.96MHz. I also assigned fifo_wr_sync on the first captured sample of each chirp to make shure the software (GNU Radio with iio device source over network) starts reading the first sample.
The problem is, that the window suddenly jumps around a number of samples. It seems to have a relation to the assignment of the fifo_wr_overflow. But when i encrease the buffersize from 131k to 4M the overflow will no longer be assigned, but sometimes the window will jump nevertheless.
Is there a way to achieve that after an overflow the DMA synchronise the next buffer again with the fifo_wr_sync signal?