Crosscore has a new way to handling interrupts from what I used with VisualDSP.
With Crosscore and SHARC+, ISR's are installed in this manner:
adi_int_InstallHandler(INTR_SPORT0_B_DMA,DMA1_HANDLER,0,true); // I2S
adi_int_InstallHandler(INTR_TIMER0_TMR5,TMR5_HANDLER,0,true); // timer
adi_int_InstallHandler(INTR_TWI0_DATA, TWI_Slave_ISR, (int*)TWIBuffer, true); // TWI
Now, how to get finer control. For example, I want I2S to have highest priority, and the ISR should not be interruptable. Next priority is the timer, and that ISR can be interrupted by I2S but not TWI. Well you get the idea. How is this configured in C source code for the Crosscore environment?