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Maximum Clock Rate (SCLK) for AD9106

Question asked by kaplox on Mar 13, 2018
Latest reply on Mar 13, 2018 by kaplox

Hi all,


Sorry of this has been previously asked, but we did not find any topic about it. We would like to ask about the Maximum Clock Rate (SCLK) of the SPI interface. In the datasheet (table 3 on page 7) it indicates that the maximum rate must be at least 80MHz. Is this correct? We want to control the AD9106 from a SPI whose clock is 50MHz. Would there be a problem?


Thank you in advance.