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Static Timing Analysis AD9122 Design

Question asked by wmaguire on Mar 13, 2018
Latest reply on Mar 16, 2018 by AdrianC

Hi there,

 

I notice that the AD9122 FMC reference design has no output delay constraints.  I think the assumption is being made that that because the design uses OSERDES devices in the FPGA, the skew between forwarded clock and data will be kept to a minimum and therefore no need to constrain the outputs.   If this is the case then as I understand it this assumption is not correct and might in some cases result in a design failing.  

 

Currently we have a AD9122 which operates correctly but fails static timing analysis (STA) for what is a relatively slow DCI clock of 103.68MHz  on a zynq design.

 

The elaborated design for the AD9122 device is shown in the attached png.  The overall trace delays to the DAC are 

1.287nSec with a 1%  or 12.87ps worst case variation between signals.  

 

With the above spec the associated constraints are as follows;

#Define Source Synchronous Clock, note the clock is the mmcm clock used in the ADI reference design.

create_generated_clock -name dac_clk_ext -source [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk] -multiply_by 1 [get_ports TX_DAC_DCIP]

 

#DC Delay = 11, input and output constraints.

#set tsu_r -0.47 # destination device setup time requirement for rising edge
#set thd_r 1.38; # destination device hold time requirement for rising edge
#set tsu_f -0.47; # destination device setup time requirement for falling edge
#set thd_f 1.38 # destination device hold time requirement for falling edge
#set trce_dly_max 12.87ps # maximum board trace relative delay
#set trce_dly_min -12.87ps; # minimum board trace relative delay

 


set_output_delay -clock dac_clk_ext -max -0.457 [get_ports {TX_DAC_DP[*]}]
set_output_delay -clock dac_clk_ext -min -1.4 [get_ports {TX_DAC_DP[*]}]
set_output_delay -clock dac_clk_ext -clock_fall -max -add_delay -0.457 [get_ports {TX_DAC_DP[*]}]
set_output_delay -clock dac_clk_ext -clock_fall -min -add_delay -1.4 [get_ports {TX_DAC_DP[*]}]

set_output_delay -clock dac_clk_ext -max -0.457 [get_ports TX_DAC_FRAMEP]
set_output_delay -clock dac_clk_ext -min -1.4 [get_ports TX_DAC_FRAMEP]
set_output_delay -clock dac_clk_ext -clock_fall -max -add_delay -0.457 [get_ports TX_DAC_FRAMEP]
set_output_delay -clock dac_clk_ext -clock_fall -min -add_delay -1.4 [get_ports TX_DAC_FRAMEP]

 

#The multi cycle below constraints are needed to make sure the correct clock edges are being analysed.   See Altera AN433 for details.

 

set_multicycle_path 0 -from [get_clocks -of_objects [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk]] -to [get_clocks dac_clk_ext]
set_false_path -setup -rise_from [get_clocks -of_objects [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk]] -fall_to [get_clocks dac_clk_ext]; # diable a)
set_false_path -setup -fall_from [get_clocks -of_objects [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk]] -rise_to [get_clocks dac_clk_ext]; # diable b)

set_multicycle_path -1 -hold -from [get_clocks -of_objects [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk]] -to [get_clocks dac_clk_ext]
set_false_path -hold -rise_from [get_clocks -of_objects [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk]] -rise_to [get_clocks dac_clk_ext];
set_false_path -hold -fall_from [get_clocks -of_objects [get_pins AD9122_Interface_i/axi_ad9122_0/inst/i_if/i_serdes_clk/clk]] -fall_to [get_clocks dac_clk_ext];

 

Unfortunately with the above constraints set,  our design fails timing with a worst case slack of -136 ps.

 

I will repeat the exercise for the AD9122 reference design to see if it passes but will have to assume zero trace delays as I don't have the data.

 

Regards

 

 

Walter

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