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AD9467 FMC Input Constraints

Question asked by wmaguire on Mar 12, 2018
Latest reply on Mar 13, 2018 by andrei_g

Hi all,


I had a look at the associated constraints files for the AD9467 FMC reference design and note that there are no input constraints specified.  


Using the Vivado timing constraints wizard the tool is looking for the rising and falling clock edge data output.


Looking at the ADI datasheet this would appear to be supplied as tskew.  Is this correct?