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AD9208 : Please check the register settings.

Question asked by ysuzuki on Mar 12, 2018

Hello.


Our customer is going to use AD9208 with DDC mode and he is developping with ALTERA A10-GX Development board.
But we have some trouble.
The recieved data in FPGA has some distortion and spike.
The code of the spikes is 1000decimal ~ 2500decimal.
And the distortion frequency is 750MHz and 1.5GHz and the amplitude is about 330decimal p-p.
I suspicious that the eye diagram may be narrow, but I'd like to confirm whether the settings of register is true ot not, at first.
Please check the following register settings.

 

[Outline of Configuration]
  Signal input channel : Ch.A only
  DDC0 input : Ch.A.
  DDC mode : Variable IF Mode
  DDC Filter : HB1
  DDC Output: Complex
  Fs : 3GHz
  CLK input : 6GHz (Divider = 2)
  IF : 750MHz
  Num. of Lane : 8
  Lane rate : 7.5Gbps

 

 

 

[Register Settings]

 

0x0002 < 0x00    ;# Normal Mode(Power Up)

 

0x0000 < 0x81    ;# write 0x81 to interface config A register to soft reset the device

 

0x0001 < 0x02    ;#Data path soft reset

 

0x0040 < 0xBF    ;# Power Down Pin Ignored
0x003F < 0x80    ;# Power Down Ignored

 

0x0571 < 0x15    ;# write 0x15 to JESD204B Link Mode Control 1 register to power down the link
0x058B < 0x07    ; #disable scrambler, L=8
0x058C < 0x00    ; #F=1
0x058D < 0x1F    ; #K=32
0x058E < 0x01    ; #M=2
0x058F < 0x0F    ; #N=16
0x0590 < 0x0F    ; #N_Prime=16

 

0x0200 < 0x00    ;# Bit[5]:Chip Q I Ignore, Bits[3:0]:Chip application Mode
0x0201 < 0x00    ;# write 0x00 to chip decimation ratio register 0x0201 for full sample rate

 

0x0570 < 0xFF     ; disable x4 mode

 

   master_write_32 $master_path [expr $base_address + 0x04] [expr 0x05900F | (($SB_val)<<5)];
0x058F < 0x0D    ;# write 0x0D to parameter CS/N register 0x058F for CS=0, N=14 config

 

#Lane powerdown
0x05B0 < 0x00    ;# write 0xF0 to lane power down register 0x05B0 for serdout 0-3 on
0x05B2 < 0x01    ;# serdout 1 = logical lane 0 , serdout 0 = logical lane 1 < swapped due to use AreiaX-GX Dev. Bd.
0x05B3 < 0x32    ;# serdout 3 = logical lane 3 , serdout 2 = logical lane 2
0x05B5 < 0x54    ;# serdout 5 = logical lane 5 , serdout 4 = logical lane 4
0x05B6 < 0x76    ;# serdout 7 = logical lane 7 , serdout 6 = logical lane 6

 

0x056E < 0x00    ;# write 0x10 to lane rate control register 0x056E for 3.1 25 <= data rate <= 6.25Gbps
0x0120 < 0x02    ;# write 0x04 to Sysref Control 1 register 0x0120 --0x04 for N shot, --0x02 for continuous sysref
0x0550 < 0x00    ;# write 0x0F to ADC Test Modes register 0x0550 -- 0x0F for ramp test pattern -- 0x06 for PN short test sequence

 

# JESD204B
0x0573 < 0x00    ;# test mode disable

 

# PFILT setup
0x0008 < 0x01     ;#.... Ch.A select
0x0DF8 < 0x00     ;#.... Disable programable filter
0x0008 < 0x02     ;#.... Ch.B select
0x0DF8 < 0x00     ;#.... Disable programable filter

 

# DDC0 setup
0x0200 < 0x01     ;#.... Chip mode : Both Real(I) and Complex(Q) selected , One DDC mode
0x0201 < 0x01     ;#.... Chip decimation ratio : Decimated by 2
0x0310 < 0x63     ;#.... DDC0 control : Real Input , 6dB Gain , Zero IF , HB1 decimated by 2
0x0311 < 0x05     ;#.... DDC0-I Input : Ch.B , DDC0-Q Input : Ch.B(A to 00)

 

# NCO0 setup
0x0314 < 0x00     ;#.... Select NCO0 to DDC0

 

# fs=3GHz , fc=750MHz(1/2 nyquist freq.)
0x0316 < 0x00     ;
0x0317 < 0x00     ;
0x0318 < 0x00     ;
0x0319 < 0x00     ;
0x031A < 0x40     ;
0x031B < 0x00     ;

 


0x0573 < 0x00    ;# Alllows injection of PRBS pattern into physical layer

 

0x0108 < 0x01    ;# input clk div 2
0x0571 < 0x14    ;# write 0x14 to JESD204B Link Mode Control 1 register to power up the link

 

0x1228 < 0x4F    ;#
0x1228 < 0x0F    ;#
0x1222 < 0x00    ;#
0x1222 < 0x04    ;#
0x1222 < 0x00    ;#
0x1262 < 0x08    ;#
0x1262 < 0x00    ;#

 


If you need more information, please let me know.

 


Best regards,
ysuzuki

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