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ADSP BF 548 clock configuration

Question asked by amar26121993 on Mar 12, 2018
Latest reply on Mar 16, 2018 by Jithul_Janardhanan

Hi everybody

Iam using ADSP BF 548 evaluation board, i tried to run the processor at 400MHZ,i.e configuring the core clock and system clock at 400MHZ.
in order to derive system clock i put the divider as 1 i.e SCLK=(CCLK/PLL_DIV)===(400MHZ/1=400MHZ).but my code is always held up in fatal exception.
the code snippet for clock configuration is as follow.

void sysconfig(void)
{
u16 SiliconRev=0;
Get_Silicon_Rev(&SiliconRev);

if( SiliconRev == BF548_REV_0_0 )
{
*pPLL_CTL = 0x2000;
idle();

*pPLL_DIV = 0x3; //SCLK=(CCLK/*pPLL_DIV)===(400MHZ/3=133MHZ) voltage to 1.25v
ssync();

*pVR_CTL = 0x40EB;
ssync();

idle();
}
else 

{
// silicon revisions of 0.1 and greater should now use bfrom_SysControl to change the PLL.
ADI_SYSCTRL_VALUES sys_cntrl_struct;

sys_cntrl_struct.uwPllCtl = 0x2000;
sys_cntrl_struct.uwPllDiv = 0x0003;
sys_cntrl_struct.uwVrCtl = 0x40EB;

bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &sys_cntrl_struct, NULL);
}

}

when the processor executes the instruction below instruction its going to exception handler
bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &sys_cntrl_struct, NULL);

Our requirement is to configure system clock at 400MHZ suggest if any other configuration to be done,
and also suggest us how to run the core clock at 533MHZ and system clock at 400MHz combination.

 

Best regards
Amar TR

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