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AD9361: Clock level in multi-chip application

Question asked by liuf_stanford on Mar 11, 2018
Latest reply on Mar 12, 2018 by liuf_stanford

We have an application that will use two synchronized AD9361s. We were planning to use the output of a 1.2V CMOS clock buffer to drive the XTAL_N pins of the two chips, but we're not sure if this is the "recommended" way to go about multi-chip synchronization since the FMCOMMS5 uses a simple capacitive divider.

 

Is there a preferred approach to MCS? If not, is 1.2V CMOS enough to cause the BB & RF PLLs to lock reliably, or should we attempt to get closer to 1.3V?

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