In reference manual of ADV7619 it says that DE_REGEN_FILTER_LOCKED bit (0x68, 0x07) should be set to get a valid horizontal measurement readback, also it says that to get a valid vertical measurement, V_LOCKED_RAW bit (0x68, 0x07) should be set.
Here is the issue; when ADV7916 receives new signal and locks its PLL on to it, it flips PLL_LOCK interrupt bit. When that occurs, we should be checking DE_REGEN_FILTER_LOCKED and V_LOCKED_RAW bits to know if we have valid measurement to get the info about coming signal, correct?
However, it our situation, it is not really correct; if we do check those valid bits, they got set, but numbers are incorrect. For some reason, we are only able to get correct measurement readback about 1 sec after PLL_LOCK interrupt received.
My question is, why is that? And, is there any other flags should we check to get valid data?