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HMC6300 and HMC6301 PLLs won't lock

Question asked by madengr on Mar 10, 2018
Latest reply on Mar 13, 2018 by madengr

I made a custom board with the HMC6300.  I'm targeting 60 GHz with a 142.8571 MHz clock for 500 MHz step size.  The problem is I can't get the PLL to lock.  Do you have more detailed documentation than the data sheet?  Typically there would be debug features, such as monitoring PLL divider output and reference input.  The data sheet alludes to it (i.e. en_test_divOut) but nothing in detail.  I'm guessing it's possible to route these to SCANOUT?

 

I can peek the registers, and everything appears programmed correctly.  The clock amplitude is good.  Supply rails are good.  Measuring 1.55 VDC on EXTFIL_N and 0.05 VDC on EXTFIL_P; assuming this is the loop filter and hitting VCC_SYN rail?  The resistors are not installed per the data sheet.  I can see the VCO drifting about 16.4 GHz with a loop probe above the chip.

 

Here are the register values:

0x00      0x00

0x01      0xCA

0x02      0xFC

0x03      0xF7

0x04      0x00

0x05      0xFF

0x06      0xEC

0x07      0x0F

0x08      0x8F

0x09      0x00

0x0A      0x50

0x0B      0xF3

0x0C      0x64

0x0D      0x00

0x0E      0x00

0x0F      0x00

0x10      0x36

0x11      0xAB   (REFCLK is AC coupled)

0x12      0x06

0x13      0x02

0x14      0x18   (divider setting for 60 GHz from table 9)

0x15      0x12

0x16      0x04   (band setting for 60 GHz from table 9)

0x17      0x62

0x18      0x87   (indicates unlocked)

0x19      0x00   (is this EXTFIL_N ?)

0x1A      0xFF   (is this EXTFIL_P ?)

0x1B      0x1F

0x1C      0x00

0x1D      0x00

0x1E      0x00

0x1F      0x87

 

I noticed that table 9 only lists 6 bits for the divider value; I'm assuming bit 6 is a zero.

 

I have an HMC6301 on the same PCB and it's exhibiting the same behavior; no lock.  

 

I'm at wits end with this thing.  Any held would be appreciated.

 

Thanks,

Lou

 

 

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