I made a custom board with the HMC6300. I'm targeting 60 GHz with a 142.8571 MHz clock for 500 MHz step size. The problem is I can't get the PLL to lock. Do you have more detailed documentation than the data sheet? Typically there would be debug features, such as monitoring PLL divider output and reference input. The data sheet alludes to it (i.e. en_test_divOut) but nothing in detail. I'm guessing it's possible to route these to SCANOUT?
I can peek the registers, and everything appears programmed correctly. The clock amplitude is good. Supply rails are good. Measuring 1.55 VDC on EXTFIL_N and 0.05 VDC on EXTFIL_P; assuming this is the loop filter and hitting VCC_SYN rail? The resistors are not installed per the data sheet. I can see the VCO drifting about 16.4 GHz with a loop probe above the chip.
Here are the register values:
0x11 0xAB (REFCLK is AC coupled)
0x14 0x18 (divider setting for 60 GHz from table 9)
0x16 0x04 (band setting for 60 GHz from table 9)
0x18 0x87 (indicates unlocked)
0x19 0x00 (is this EXTFIL_N ?)
0x1A 0xFF (is this EXTFIL_P ?)
I noticed that table 9 only lists 6 bits for the divider value; I'm assuming bit 6 is a zero.
I have an HMC6301 on the same PCB and it's exhibiting the same behavior; no lock.
I'm at wits end with this thing. Any held would be appreciated.