Can someone please clarify the 't8 max' time specified in the UM. I read it as the FSYNC must go high 10 to 20 ns after the last clock pulse.
1. Is this applicable even if there are no more clock pulses after the last clock/data bit?
2. What happens if FSYNC does not go high within this time, is the data ignored/discarded?
This very stringent timing requirement (10 to 20ns) makes it virtually impossible to implement the SPI communication using bit-banging. My implementation would use bit-banging, send one command every 100 ms and in-between not send out any clock pulses. Please clarify if this is possible at all. Thanks!